The data is processed by video pipeline and passed back to the host system via PCIe. In this design, the input of the video processing pipeline is generated by an application on the host computer at 1080p60 resolution and transmitted to the ZC706 board via PCIe. In the Base Targeted Reference design, the input of the video processing pipeline is generated by a test pattern generator in the FPGA fabric. For additional information, refer to UG961.ġ.1 About the Zynq PCIe TRD The Zynq PCIe Targeted reference design expands the Base Targeted Reference Design (UG925) by adding PCI Express communication with a host system at PCIe x4 GEN2 speed. The ZC706 Evaluation kit is based on a XC7Z045 FFG900-2 Zynq-7000 SoC device. ISE DS 14.3 Zynq PCIe Targeted Reference Designġ Introduction This page provides instructions on how to build various components of the Zynq PCIe Targeted Reference Design (TRD) and how to setup the hardware platform and run the design on the ZC706 Evaluation Kit.

ISE DS 14.4 Zynq PCIe Targeted Reference Design ISE DS 14.5 Zynq PCIe Targeted Reference Design ISE DS 14.6 Zynq PCIe Targeted Reference Design

Xilinx ise 14.7 xp